AS4LC256K16E0 - 3.3V 256K X 16 CMOS DRAM (EDO)

Alliance Semiconductor

AS4LC256K16E0 Datasheet Preview — Preview of AS4LC256K16E0 PDF

Datasheet Details

Part number	AS4LC256K16E0
Manufacturer	Alliance Semiconductor
File Size	812.87 KB
Description	3.3V 256K X 16 CMOS DRAM (EDO)
Datasheet	AS4LC256K16E0_AllianceSemiconductor.pdf

AS4LC256K16E0 Product details

Description

Address inputs Row address strobe Input/output Output enable Column address strobe, upper byte Column address strobe, lower byte Read/write control Power (3.3V ± 0.3V) Ground I/O6 I/O7 NC NC WE RAS NC A0 A1 A2 AS4LC256K16EO I/O9 I/O8 NC LCAS UCAS OE A8 A7 A6 A5 AS4LC256K16EO 1 2 3 4 5 6 7 8 9 10 13 14 15 16 17 18 19 20 21 22 DataShee LCAS 32 31 30 29 28 27 26 25 24 23 NC LCAS UCAS OE WE VCC GND A3 Vcc A4 GND NC A0 A1 A2 A3 VCC A8 A7 A6 A5 A4 GND Selection guide Symbol Maximum RAS ac

Features

Organization: 262,144 words × 16 bits.
High speed - 45/60 ns RAS access time - 10/12/15/20 ns column address access time - 7/10/10 ns CAS access time.
Low power consumption.
EDO page mode.
5V I/O tolerant.
512 refresh cycles, 8 ms refresh interval - RAS-only or CAS-before-RAS refresh or self refresh.
Read-modify-write.
LVTTL-compatible, three-state I/O.
JEDEC standard packages - Active: 280 mW max (AS4LC256K16E.

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Published: Sep 20, 2006 |