CY7C1372D - 18-Mbit (512 K 횞 36/1 M 횞 18) Pipelined SRAM

Cypress

Datasheet Details

Pin-compatible and functionally equivalent to ZBT™.
Supports 250-MHz bus operations with zero wait states.
Available speed grades are 250, 200, and 167 MHz.
Internally self-timed output buffer control to eliminate the need to use asynchronous OE.
Fully registered (inputs and outputs) for pipelined operation.
Byte write capability.
3.3 V core power supply (VDD).
3.3 V/2.5 V I/O power supply (VDDQ).
Fast clock-to-output times.
2.6 ns (for 250 MHz.

📁 CY7C1372D Similar Datasheet

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Other Datasheets by Cypress

CY7C1372C - 512K x 36/1M x 18 Pipelined SRAM with NoBL Architecture
CY7C1372CV25 - 512K x 36/1M x 18 Pipelined SRAM with NoBL Architecture
CY7C1370C - 512K x 36/1M x 18 Pipelined SRAM with NoBL Architecture
CY7C1370CV25 - 512K x 36/1M x 18 Pipelined SRAM with NoBL Architecture
CY7C1370D - 18-Mbit (512 K 횞 36/1 M 횞 18) Pipelined SRAM
CY7C1371C - 18-Mbit (512K x 36/1M x 18) Flow-Through SRAM with NoBL Architecture

Published: Aug 19, 2005 |