CY7C1372B, CY7C1370B Datasheet (Cypress Semiconductor) - (CY7C1370B / CY7C1372B) 512K X 36/1M X 18 Pipelined SRAM

CY7C1372B, CY7C1370B, (CY7C1370B / CY7C1372B) 512K X 36/1M X 18 Pipelined SRAM

The CY7C1370B and CY7C1372B SRAMs are designed to eliminate dead cycles when transitions from Read to Write or vice versa.

These SRAMs are optimized for 100 percent bus utilization and achieve Zero Bus Latency.

They integrate 524,288 × 36 and 1,048,576 × 18 SRAM cells, respectively, with advanced sy

CY7C1372B Features

* Zero Bus Latency, no dead cycles between Write and Read cycles

* Fast clock speed: 200, 167, 150, and 133 MHz

* Fast access time: 3.0, 3.4, 3.8, and 4.2 ns

* Internally synchronized registered outputs eliminate the need to control OE

* Single 3.3V

* 5