CY7C1417AV18 - 1.8V Synchronous Pipelined SRAM

Cypress Semiconductor

Datasheet Details

Part number	CY7C1417AV18
Manufacturer	Cypress Semiconductor
File Size	434.16 KB
Description	1.8V Synchronous Pipelined SRAM
Datasheet	CY7C1417AV18-CypressSemiconductor.pdf

36-Mbit density (4M x 8, 4M x 9, 2M x 18, 1M x 36).
300-MHz clock for high bandwidth.
4-Word burst for reducing address bus frequency.
Double Data Rate (DDR) interfaces (data transferred at 600 MHz) @ 300 MHz.
Two input clocks (K and K) for precise DDR timing.
SRAM uses rising edges only.
Two input clocks for output data (C and C) to minimize clock-skew and flight-time mismatches.
Echo clocks (CQ and CQ) simplify data captu.

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Published: Nov 6, 2016 |