CY7C1460SV25 Datasheet (Cypress) - 36-Mbit (1M x 36/2M x 18) Pipelined SRAM

CY7C1460SV25, 36-Mbit (1M x 36/2M x 18) Pipelined SRAM

The CY7C1460SV25/CY7C1462SV25 are 2.5 V, 1M × 36/2M × 18 Synchronous pipelined burst SRAMs with No Bus Latency™ (NoBL logic, respectively.

They are designed to support unlimited true back to back Read/Write operations with no wait states.

The CY7C1460SV25/CY7C1462SV25 are equipped with the advance

CY7C1460SV25 Features

* Pin compatible and functionally equivalent to ZBT™

* Supports 250-MHz bus operations with zero wait states

* Available speed grades are 250 and 167 MHz

* Internally self-timed output buffer control to eliminate the need to use asynchronous OE

* Fully registered (inputs and outp