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CY7C1021BV33 - 64K x 16 Static RAM

Download the CY7C1021BV33 datasheet PDF. This datasheet also covers the CY7 variant, as both devices belong to the same 64k x 16 static ram family and are provided as variant models within a single manufacturer datasheet.

Description

of read and write modes.

The input/output pins (I/O1 through I/O16) are placed in a high-impedance state when the device is deselected (CE HIGH), the outputs are disabled (OE HIGH), the BHE and BLE are disabled (BHE, BLE HIGH), or during a write operation (CE LOW, and WE LOW).

Features

  • 3.3V operation (3.0V.
  • 3.6V).
  • High speed.
  • tAA = 10/12/15 ns.
  • CMOS for optimum speed/power.
  • Low Active Power (L version).
  • 576 mW (max. ).
  • Low CMOS Standby Power (L version).
  • 1.80 mW (max. ).
  • Automatic power-down when deselected.
  • Independent control of upper and lower bits.
  • Available in 44-pin TSOP II and 400-mil SOJ.
  • Available in a 48-Ball Mini BGA package Writing to the device is acco.

📥 Download Datasheet

Note: The manufacturer provides a single datasheet file (CY7-C1021B.pdf) that lists specifications for multiple related part numbers.

📁 Similar Datasheet

Part Number Description Manufacturer
CY7C1006D 1-Mbit (256K x 4) Static RAM Cypress
CY7C1011G 2-Mbit (128K words x 16 bit) Static RAM Cypress
CY7C1041G 4-Mbit (256K words x 16 bit) Static RAM Cypress
CY7C1041GE 4-Mbit (256K words x 16 bit) Static RAM Cypress
CY7C1041GN 4-Mbit (256K words x 16 bit) Static RAM Cypress

Other Datasheets by Cypress (Infineon)

Part Number Description
CY7C1021BN 1-Mbit (64 K x 16) Static RAM
CY7C1021 64K x 16 Static RAM
CY7C10212CV33 1-Mbit (64 K x 16) Static RAM
CY7C1021CV26 1-Mbit (64K x 16) Static RAM
CY7C1021CV33 64K x 16 Static RAM

Full PDF Text Transcription (Reference)

The following content is an automatically extracted verbatim text from the original manufacturer datasheet and is provided for reference purposes only.

View original datasheet text
021BV33 CY7C1021BV33 64K x 16 Static RAM Features • 3.3V operation (3.0V–3.6V) • High speed — tAA = 10/12/15 ns • CMOS for optimum speed/power • Low Active Power (L version) — 576 mW (max.) • Low CMOS Standby Power (L version) — 1.80 mW (max.) • Automatic power-down when deselected • Independent control of upper and lower bits • Available in 44-pin TSOP II and 400-mil SOJ • Available in a 48-Ball Mini BGA package Writing to the device is accomplished by taking Chip Enable (CE) and Write Enable (WE) inputs LOW. If Byte Low Enable (BLE) is LOW, then data from I/O pins (I/O1 through I/O8), is written into the location specified on the address pins (A0 through A15).
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