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CY7C1021 - 64K x 16 Static RAM

Download the CY7C1021 datasheet PDF. This datasheet also covers the CY7 variant, as both devices belong to the same 64k x 16 static ram family and are provided as variant models within a single manufacturer datasheet.

Description

of read and write modes.

The input/output pins (I/O1 through I/O16) are placed in a high-impedance state when the device is deselected (CE HIGH), the outputs are disabled (OE HIGH), the BHE and BLE are disabled (BHE, BLE HIGH), or during a write operation (CE LOW, and WE LOW).

Features

  • High speed.
  • tAA = 12 ns.
  • CMOS for optimum speed/power.
  • Low active power.
  • 1320 mW (max. ).
  • Automatic power-down when deselected.
  • Independent Control of Upper and Lower bits.
  • Available in 44-pin TSOP II and 400-mil SOJ (BLE) is LOW, then data from I/O pins (I/O1 through I/O8), is written into the location specified on the address pins (A0 through A15). If Byte High Enable (BHE) is LOW, then data from I/O pins (I/O9 through I/O.

📥 Download Datasheet

Note: The manufacturer provides a single datasheet file (CY7-C1021.pdf) that lists specifications for multiple related part numbers.

📁 Similar Datasheet

Part Number Description Manufacturer
CY7C1006D 1-Mbit (256K x 4) Static RAM Cypress
CY7C1011G 2-Mbit (128K words x 16 bit) Static RAM Cypress
CY7C1041G 4-Mbit (256K words x 16 bit) Static RAM Cypress
CY7C1041GE 4-Mbit (256K words x 16 bit) Static RAM Cypress
CY7C1041GN 4-Mbit (256K words x 16 bit) Static RAM Cypress

Other Datasheets by Cypress (Infineon)

Part Number Description
CY7C10212CV33 1-Mbit (64 K x 16) Static RAM
CY7C1021BN 1-Mbit (64 K x 16) Static RAM
CY7C1021BV33 64K x 16 Static RAM
CY7C1021CV26 1-Mbit (64K x 16) Static RAM
CY7C1021CV33 64K x 16 Static RAM

Full PDF Text Transcription

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021 CY7C1021 64K x 16 Static RAM Features • High speed — tAA = 12 ns • CMOS for optimum speed/power • Low active power — 1320 mW (max.) • Automatic power-down when deselected • Independent Control of Upper and Lower bits • Available in 44-pin TSOP II and 400-mil SOJ (BLE) is LOW, then data from I/O pins (I/O1 through I/O8), is written into the location specified on the address pins (A0 through A15). If Byte High Enable (BHE) is LOW, then data from I/O pins (I/O9 through I/O16) is written into the location specified on the address pins (A0 through A15). Reading from the device is accomplished by taking Chip Enable (CE) and Output Enable (OE) LOW while forcing the write enable (WE) HIGH.
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