PA7572 Datasheet (Anachip) - Programmable Electrically Erasable Logic

PA7572, Programmable Electrically Erasable Logic

The PA7572 is a member of the Programmable Electrically Erasable Logic (PEEL™) Array family based on Anachip’s CMOS EEPROM technology.

PEEL™ Arrays free designers from the limitations of ordinary PLDs by providing the architectural flexibility and speed needed for today’s programmable logic designs.

PA7572 PEEL Array™ Programmable Electrically Erasable Logic Array Versatile Logic Array Architecture - 24 I/Os, 14 inputs, 60 registers/latches - Up to 72 logic cell output functions - PLA structure with true product-term sharing - Logic functions and registers can be I/O-buried High-Speed Commercial and Industrial Versions - As fast as 13ns/20ns (tpdi/tpdx), 66.6MHz (fMAX) - Industrial grade available for 4.5 to 5.5V VCC and -40 to +85 °C temperatures www.DataSheet4U.com Ideal for Combinatorial

PA7572 Features

* - Independent or global clocks, resets, presets, clock polarity and output enables - Sum-of-products logic for output enables Development and Programmer Support - ICT PLACE Development Software - Fitters for ABEL, CUPL and other software - Programming support by popular third-party programmers Gene