PA7128 Datasheet (Integrated Circuit Technology) - Programmable Electrically Erasable Logic Array

PA7128, Programmable Electrically Erasable Logic Array

The PA7128 is a member of the Programmable Electrically Erasable Logic (PEEL™) Array family based on ICT’s CMOS EEPROM technology.

PEEL™ Arrays free designers from the limitations of ordinary PLDs by providing the architectural flexibility and speed needed for today’s programmable logic designs.

The

PA7128 Features

* s CMOS Electrically Erasable Technology

* Reprogrammable in 28-pin DIP , SOIC and PLCC packages Versatile Logic Array Architecture

* 12 I/Os, 14 inputs, 36 registers/latches

* Up to 36 logic cell output functions

* PLA structure with true product-term sharing