The following content is an automatically extracted verbatim text
from the original manufacturer datasheet and is provided for reference purposes only.
View original datasheet text
March 2001
®
5V/3.3V 128K×8 CMOS SRAM (Evolutionary Pinout)
AS7C1024 AS7C31024
Features
• AS7C1024 (5V version) • AS7C31024 (3.3V version) • Industrial and commercial temperatures • Organization: 131,072 words × 8 bits • High speed
- 12/15/20 ns address access time - 6,7,8 ns output enable access time • Low power consumption: ACTIVE - 825 mW (c) / max @ 12 ns - 360 mW (AS7C31024) / max @ 12 ns • Low power consumption: STANDBY - 55 mW (AS7C1024) / max CMOS - 36 mW (AS7C31024) / max CMOS
• 2.0V data retention • Easy memory expansion with CE1, CE2, OE inputs • TTL/LVTTL-compatible, three-state I/O • 32-pin JEDEC standard packages
- 300 mil SOJ - 400 mil SOJ - 8 × 20mm TSOP I - 8 × 13.