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AS7C1024 - 5V/3.3V 128K × 8 CMOS SRAM

Download the AS7C1024 datasheet PDF. This datasheet also covers the AS7C31024 variant, as both devices belong to the same 5v/3.3v 128k × 8 cmos sram family and are provided as variant models within a single manufacturer datasheet.

Features

  • AS7C1024 (5V version).
  • AS7C31024 (3.3V version).
  • Industrial and commercial temperatures.
  • Organization: 131,072 words × 8 bits.
  • High speed - 12/15/20 ns address access time - 6,7,8 ns output enable access time.
  • Low power consumption: ACTIVE - 825 mW (c) / max @ 12 ns - 360 mW (AS7C31024) / max @ 12 ns.
  • Low power consumption:.

📥 Download Datasheet

Note: The manufacturer provides a single datasheet file (AS7C31024-AllianceSemiconductorCorporation.pdf) that lists specifications for multiple related part numbers.

Datasheet Details

Part number AS7C1024
Manufacturer Alliance Semiconductor
File Size 117.55 KB
Description 5V/3.3V 128K × 8 CMOS SRAM
Datasheet download datasheet AS7C1024 Datasheet

Full PDF Text Transcription (Reference)

The following content is an automatically extracted verbatim text from the original manufacturer datasheet and is provided for reference purposes only.

View original datasheet text
March 2001 ® 5V/3.3V 128K×8 CMOS SRAM (Evolutionary Pinout) AS7C1024 AS7C31024 Features • AS7C1024 (5V version) • AS7C31024 (3.3V version) • Industrial and commercial temperatures • Organization: 131,072 words × 8 bits • High speed - 12/15/20 ns address access time - 6,7,8 ns output enable access time • Low power consumption: ACTIVE - 825 mW (c) / max @ 12 ns - 360 mW (AS7C31024) / max @ 12 ns • Low power consumption: STANDBY - 55 mW (AS7C1024) / max CMOS - 36 mW (AS7C31024) / max CMOS • 2.0V data retention • Easy memory expansion with CE1, CE2, OE inputs • TTL/LVTTL-compatible, three-state I/O • 32-pin JEDEC standard packages - 300 mil SOJ - 400 mil SOJ - 8 × 20mm TSOP I - 8 × 13.
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