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Zarlink Semiconductor

MT90223 Datasheet Preview

MT90223 Datasheet

4/8/16 Port IMA/TC PHY Device

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Features
IMA
• Up to 16 T1, E1, J1, DSL links & up to 8 IMA
groups with 1 to 16 links/IMA group1
• Supports symmetrical & asymmetrical operation
• CTC (common transmit) & ITC (independent
transmit) clocking modes
• Pre-processing of RX ICP (IMA control protocol)
www.DatacSehlelset4U.com
• IMA layer & per link statistics and alarms for
performance monitoring with MIB support
TC and UNI
• Supports mixed-mode operation: links not
assigned to an IMA group can be used in TC
mode
• ATM framing using cell delineation
1. MT90222 supports up to 4 serial links with maximum 4 groups
to be used - groups 0,1,2,3.
MT90223 supports up to 8 serial links
MT90224 supports up to 16 serial links
RX External Static RAM
MT90222/3/4
4/8/16 Port IMA/TC PHY Device
Data Sheet
March 2006
Ordering Information
MT90222AG
MT90224AG
MT90223AG
MT90223AG2
MT90224AG2
384 Pin PBGA
384 Pin PBGA
384 Pin PBGA
384 Pin PBGA**
384 Pin PBGA**
Trays
Trays
Trays
Trays
Traus
**Pb Free Tin/Silver/Copper
-40°C to +85°C
• HEC (header error control) verification &
generation, error detection, filler cell filtering (IMA
mode) and idle/unassigned cell filtering (TC
mode)
• TC layer statistics and error counts i.e. HEC
errors with MIB support
Standards Compliant
• ATM Forum - IMA 1.1 (AF-PHY-0086.001) &
backwards compatible with IMA 1.0
• ATM Forum - ATM over Fractional T1/E1 (AF-
PHY-0130.00)
• ITU G.804 cell mapping & ITU I.432 cell
delineation
TDM Ring
RX
Utopia
Level 2
BUS
TX
Rx Utopia
FIFo
Utopia
I/F CTRL
Internal IMA
Processors
(1 per group)
TDM
Ring
Control
S/P
Cell
Delineator
CD Circuits (1 per link)
T1/E1/DSL
T1/E1/DSL
Tx Utopia
FIFo
Processor I/F
Transmission
Convergence
TC Circuits (1 per link)
P/S
TDM
Ring
Control
T1/E1/DSL
Serial TDM Ports
(1 per link, up to 10Mb/s
per link)
TDM Ring
Figure 1 - MT90222/3/4 Block Diagram (with Built-in IMA functions for up to 8 IMA Groups over
4/8/16 links)
1
Zarlink Semiconductor Inc.
Zarlink, ZL and the Zarlink Semiconductor logo are trademarks of Zarlink Semiconductor Inc.
Copyright 2004-2006, Zarlink Semiconductor Inc. All Rights Reserved.




Zarlink Semiconductor

MT90223 Datasheet Preview

MT90223 Datasheet

4/8/16 Port IMA/TC PHY Device

No Preview Available !

MT90222/3/4
Data Sheet
General
• Supports unframed serial streams up to 10 Mb/s per T1/E1 or DSL link
• Single chip ATM IMA & TC processor
• Versatile TDM interface for most popular T1 or E1 framers and DSL chipsets
• Up to 6 MT90222/3/4 devices can be spanned using a TDM ring supporting 32 links
• Provides 8 & 16-bit UTOPIA Level 1 & 2 compatible MPHY Interface (MT90222/3/4 slaved to ATM device)
• 16-bit microprocessor interface for Intel or Motorola
• JTAG test support
• 2.5 V core, 3.3 V I/O with 5 V tolerant inputs
• 384 pin PGBA with 1.0 mm pitch balls
www.DataMShTe9e0t42U2.2c,omMT90223 & MT90224 share the same product package and pin-out configuration
Applications
Provides cost effective solutions to implement IMA and/or TC functions over T1, E1, J1 or DSL transport facilities in
broadband access networks. Typical applications are for trunking or subscriber access in:
• Integrated multi-service access platforms
• Access multiplexers
• Next-generation DLC
• Wireless local loop
• 3G wireless base-stations
Preamble
The MT90222, MT90223 and MT90224 form a family of similar devices, differing mainly in the maximum number of
serial links, and are collectively referred to as MT90222/3/4. It should be noted throughout this document whenever
reference is made to the number of serial links that the MT90224 offers a maximum of 16 serial links (links 15:0),
while the MT90223 offers a maximum of 8 serial links (links 14,12,10,8,6,4,2 and 0), and the MT90222 offers a
maximum of 4 serial links (links 12, 8, 4 and 0). Pin and register compatibility has been maintained to offer
interchangeability.
Note: When creating IMA groups for MT90222 the groups 0, 1, 2 and 3 should be used.
Description
The MT90222/3/4 device is targeted to systems implementing the ATM FORUM Inverse Multiplexing for ATM (IMA
version 1.1 and 1.0) or UNI specifications for T1/E1 rates. In the MT90222/3/4 architecture, up to 16 physical and
independent serial links can be terminated through the utilization of off-the-shelf, traditional T1/E1/J1 framers/LIUs
and DSL chip sets. The MT90222/3/4 device can also provide up to 10 Mb/s per link data rates for unframed serial
TDM transmissions for xDSL applications.
The MT90222/3/4 device provides ATM system designers with a flexible architecture when implementing ATM
access over existing trunk interfaces, allowing a migration towards ATM service technology. In addition to the
design of ATM UNI specifications for T1/E1 rates, the MT90222/3/4 device is compliant with the ATM FORUM IMA
specifications for controlling IMA groups of up to 16 trunks in a single chip. The MT90222/3/4 can be configured to
operate in different modes to facilitate the implementation of the IMA function at both CPE and Central Office sites.
For systems targeting ATM over T1/E1 with IMA and TC operating simultaneously, the MT90222/3/4 device
provides the ideal architecture and capabilities.
2
Zarlink Semiconductor Inc.


Part Number MT90223
Description 4/8/16 Port IMA/TC PHY Device
Maker Zarlink Semiconductor
Total Page 30 Pages
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