CY2SSTV16859 datasheet, buffer equivalent, SpectraLinear

Features and benefits

* Differential clock inputs up to 280 MHz
* Supports LVTTL switching levels on the RESET# pin
* Output drivers have controlled edge rates, so no external resi.

Description

This 13-bit to 26-bit registered buffer is designed for 2.3V to 2.7 VDD operations. All inputs are compatible with the JEDEC Standard for SSTL-2, except the LVCMOS reset (RESET#) input. All outputs are SSTL_2, Class II compatible. Block Diagram Pin.

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