CY2SSTV855 buffer/driver equivalent, differential clock buffer/driver.
* Phase-locked loop (PLL) clock distribution for Double Data Rate Synchronous DRAM applications
* 1:5 differential outputs
* External feedback pins (FBINT, FB.
* 1:5 differential outputs
* External feedback pins (FBINT, FBINC) are used to
synchronize the outputs to the cl.
The CY2SSTV855 is a high-performance, very-low-skew, very-low-jitter zero-delay buffer that distributes a differential clock input pair (SSTL_2) to four differential (SSTL_2) pairs of clock outputs and one differential pair of feedback clock outputs..
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