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CY2SSTV857-32 - Differential Clock Buffer/Driver DDR400/PC3200-Compliant

General Description

The CY2SSTV857-32 is a high-performance, low-skew, low-jitter zero-delay buffer designed to distribute differential clocks in high-speed applications.

The CY2SSTV857-32 generates ten differential pair clock outputs from one differential pair clock input.

Key Features

  • Operating frequency: 60 MHz to 230 MHz.
  • Supports 400 MHz DDR SDRAM.
  • 10 differential outputs from one differential input.
  • Spread-Spectrum-compatible.
  • Low jitter (cycle-to-cycle): < 75.
  • Very low skew: < 100 ps.
  • Power management control input.
  • High-impedance outputs when input clock < 20 MHz.
  • 2.6V operation.
  • Pin-compatible with CDC857-2 and -3.
  • 48-pin TSSOP and 40 QFN package.
  • Industrial tem.

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Full PDF Text Transcription (Reference)

The following content is an automatically extracted verbatim text from the original manufacturer datasheet and is provided for reference purposes only.

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CY2SSTV857-32 Differential Clock Buffer/Driver DDR400/PC3200-Compliant Features • Operating frequency: 60 MHz to 230 MHz • Supports 400 MHz DDR SDRAM • 10 differential outputs from one differential input • Spread-Spectrum-compatible • Low jitter (cycle-to-cycle): < 75 • Very low skew: < 100 ps • Power management control input • High-impedance outputs when input clock < 20 MHz • 2.6V operation • Pin-compatible with CDC857-2 and -3 • 48-pin TSSOP and 40 QFN package • Industrial temperature of –40°C to 85°C • Conforms to JEDEC DDR specification Description The CY2SSTV857-32 is a high-performance, low-skew, low-jitter zero-delay buffer designed to distribute differential clocks in high-speed applications.