CY2SSTV850 buffer/driver equivalent, differential clock buffer/driver.
* Phase-locked loop clock distribution for Double Data Rate Synchronous DRAM applications
* 1:10 differential outputs
* External Feedback pins (FBINT, FBINC) .
* 1:10 differential outputs
* External Feedback pins (FBINT, FBINC) are used to synchronize the outputs to the c.
This PLL clock buffer is designed for 2.5 VDD and 2.5 AVDD operation and differential data input and output levels. This device is a zero-delay buffer that distributes a differential clock input pair (CLKINT, CLKINC) to ten differential pair of clock.
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