* Double-data-rate architecture; two data transfers per clock cycle
* Bidirectional data strobe(DQS)
* Four banks operation
* Differential clock inputs(CK.

SYMBOL CK, CK DDR SDRAM TYPE Input DESCRIPTION Clock : CK and CK are differential clock inputs. All address and control input signals are sampled on the positive edge of CK and negative edge of CK. Output (read) data is referenced to both edges of.

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