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K4H560838D-TCB3 - 256Mb D-die DDR Sdram

General Description

Clock : CK and CK are differential clock inputs.

All address and control input signals are sampled on the positive edge of CK and negative edge of CK.

Output (read) data is referenced to both edges of CK.

Key Features

  • Double-data-rate architecture; two data transfers per clock cycle.
  • Bidirectional data strobe(DQS).
  • Four banks operation.
  • Differential clock inputs(CK and CK).
  • DLL aligns DQ and DQS transition with CK transition.
  • MRS cycle with address key programs -. Read latency 2, 2.5 (clock) www. DataSheet4U. com -. Burst length (2, 4, 8) -. Burst type (sequential & interleave).
  • All inputs except data & DM are sampled at the positive going edge of.

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Full PDF Text Transcription for K4H560838D-TCB3 (Reference)

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256Mb Key Features • Double-data-rate architecture; two data transfers per clock cycle • Bidirectional data strobe(DQS) • Four banks operation • Differential clock inputs...

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al data strobe(DQS) • Four banks operation • Differential clock inputs(CK and CK) • DLL aligns DQ and DQS transition with CK transition • MRS cycle with address key programs -. Read latency 2, 2.5 (clock) www.DataSheet4U.com -. Burst length (2, 4, 8) -. Burst type (sequential & interleave) • All inputs except data & DM are sampled at the positive going edge of the system clock(CK) • Data I/O transactions on both edges of data strobe • Edge aligned data output, center aligned data input • LDM,UDM/DM for write masking only • Auto & Self refresh • 7.8us refresh interval(8K/64ms refresh) • Maximum burst refresh cycle : 8 • 66p

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