HYS72T512422HFN-3.7-A Datasheet, Qimonda

* Detects errors on the channel and reports them to the host memory controller.
* Automatic DDR2 DRAM Bus Calibration.
* Automatic Channel Calibration.
* .

* Module organisation two ranks 512M ×72
* JEDEC Standard Double Data Rate 2 Synchronous DRAMs (DDR2 SDRAMs) wi.

Standard High-Speed Differential Point-to-Point Link Interface at 1.5 V. The Advanced Memory Buffer also allows buffering of memory traffic to support large memory capacities. All memory control for the DRAM resides in the host, including memory requ.

HYS72T512422HFN-3S-A

HYS72T512420EFA-25F-C

HYS72T512420EFA-3S-C

HYS72T512020HR-3.7-A

HYS72T512020HR-5-A

HYS72T512022EP-3.7-B

HYS72T512022EP-3S-B

HYS72T512022HFN-3.7-A

HYS72T512022HR-3.7-A

HYS72T512022HR-3S-A

HYS72T512022HR-5-A

HYS72T512122HFN-3.7-A

HYS72T512341HHP-3.7-B