HYS72T512022HR-3S-A Datasheet, Qimonda

* Auto Refresh (CBR) and Self Refresh
* Average Refresh Period 7.8 µs at a TCASE lower than 85 °C, 3.9µs between 85 °C and 95 °C.
* All inputs and outputs SST.

* Two rank 256M × 72, 512M × 72 module organization and 2 × 128M × 8, 2 × 256M × 4 chip organization
* 2GByte, 4.

capacitive loading to the system bus, but adds one cycle to the SDRAM timing. Decoupling capacitors are mounted on the PCB board. The DIMMs feature serial presence detect based on a serial E2PROM device using the 2-pin I2C protocol. The first 128 byt.

HYS72T512022HR-3.7-A

HYS72T512022HR-5-A

HYS72T512022HFN-3.7-A

HYS72T512022EP-3.7-B

HYS72T512022EP-3S-B

HYS72T512020HR-3.7-A

HYS72T512020HR-5-A

HYS72T512122HFN-3.7-A

HYS72T512341HHP-3.7-B

HYS72T512341HHP-5-B

HYS72T512341HJP-3.7-B

HYS72T512341HJP-5-B

HYS72T512341HKP-3.7-B