PLL103-04 buffer equivalent, 1-to-4 clock distribution buffer.
4 outputs identical to FIN. Low skew (< 250 ps between outputs). Input / Output frequency range 0
– 160 MHz 25mA drive capability at TTL levels. 70mA driv.
The PLL103-04 is a 1-to-4 Clock Distribution Buffer, reproducing the reference input frequency (FIN) at 4 different outputs. It is designed to minimize skew between outputs and provides TTL and CMOS compatible output levels. An output enable selecto.
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