PLL103-05 Datasheet (PhaseLink Corporation) - 1-to-5 Clock Distribution Buffer

PLL103-05, 1-to-5 Clock Distribution Buffer

The PLL103-05 is a 1-to-5 Clock Distribution Buffer, reproducing the reference input frequency (FIN) at 5 different outputs.

It is designed to minimize skew between outputs and provides TTL and CMOS compatible output levels.

BLOCK DIAGRAM CLK1 CLK2 FIN CLK3 CLK4 CLK5 47745 Fremont Blvd., Fremont

PLL103-05 Features

* 5 outputs identical to FIN. Low skew (< 250 ps between outputs). Input / Output frequency range 0

* 160 MHz 25mA drive capability at TTL levels. 70mA drive capability at CMOS levels. 3.3V operation. Available in 8-Pin 150m