PLL103-04 Datasheet (PhaseLink Corporation) - 1-to-4 Clock Distribution Buffer

PLL103-04, 1-to-4 Clock Distribution Buffer

The PLL103-04 is a 1-to-4 Clock Distribution Buffer, reproducing the reference input frequency (FIN) at 4 different outputs.

It is designed to minimize skew between outputs and provides TTL and CMOS compatible output levels.

An output enable selector is available to tri-state all outputs.

BLOCK DI

PLL103-04 Features

* 4 outputs identical to FIN. Low skew (< 250 ps between outputs). Input / Output frequency range 0

* 160 MHz 25mA drive capability at TTL levels. 70mA drive capability at CMOS levels. Output enable mode available to tri-state all outputs. www.DataSheet4U.com

* 3.3V operation.