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PLL650-06 Datasheet Preview

PLL650-06 Datasheet

Network LAN Clock

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et4U.com PLL650-06FEATURES
heFull CMOS output swing with 40-mA output drive
taScapability. 25-mA output drive at TTL level.
aAdvanced, low power, sub-micron CMOS processes.
.D25MHz fundamental crystal or clock input.
One output fixed at 50MHz
wOne selectable frequency output of 66.6 or 75MHz (with
wDouble Drive Strength output).
wZero PPM synthesis error in all clocks.
mIdeal for Network switches.
o3.3V operation.
Available in 8-Pin 150mil SOIC.
.cDESCRIPTIONS
UThe PLL 650-06 is a low cost, low jitter, and high
t4performance clock synthesizer. With PhaseLink’s
proprietary analog Phase Locked Loop techniques, the chip
eaccepts 25.0 MHz crystal, and produces one 50MHz output
clock and one selectable 75MHz or 66.6MHz output clock,
emaking the chip ideal for networking applications.
hBLOCK DIAGRAM
Network LAN Clock
PIN CONFIGURATION
XIN
XOUT
GND
50MHz/FS*
1
2
3
4
8 VDD
7 GND
6 75MHz+/66MHz+
5 VDD
*: bi-directional pin + : double strength output
FREQUENCY TABLE
FS Pin 6
0 75MHz
1 66.6MHz
.DataSXIN
XOUT
XTAL
OSC
www omFS
Control
Logic
50MHz
1 75MHz/66MHz
www.DataSheet4U.c47745 Fremont Blvd., Fremont, California 94538 TEL (510) 492-0990 FAX (510) 492-0991
Rev 08/15/03 Page 1




PhaseLink

PLL650-06 Datasheet Preview

PLL650-06 Datasheet

Network LAN Clock

No Preview Available !

PIN DESCRIPTIONS
Name
XIN
XOUT
50MHz/FS
Number
1
2
4
75MHz / 66MHz
VDD
GND
6
5, 8
3, 7
PLL650-06
Network LAN Clock
Type
Description
I
25MHz fundamental crystal input (20pF CL parallel resonant). CL have been
integrated into the chip. No external CL capacitor is required.
I Crystal connection pin.
B
50MHz outputs. This pin latches the FS input value at power-up. It has a
60kinternal pull up resistor.
O
75MHz or 66.6MHz outputs with double drive strength. The output frequency
is determined by the value of FS (see pin 4).
P 3.3V power supply.
P Ground.
FUNCTIONAL DESCRIPTION
Selectable spread spectrum and output frequencies
The PLL650-06 provides selectable output frequencies. Selection is made by connecting the selector pin to a logical “zero” or
“one”, or by leaving it not connected (internal pull-up) according to the frequency selection table shown on page 1.
Pin 4 (FS) is a bi-directional pin used to select the output frequency of pin 6 (75MHz or 66.6MHz) according to the Frequency
Selection Table on page 1. The description of how to connect this bi-directional pin follows in the next paragraph.
Connecting a bi-directional pin
A bi-directional pin serves as input upon power-up, and as output as soon as the inputs have been latched. The value of the
input is latched-in upon power-up. Depending on the pin (see pin description), the input can be tri-level or a standard two-level.
Unlike unidirectional pins, bi-directional pins cannot be connected directly to GND or VDD in order to set the input to "0" or "1",
since the pin also needs to serve as output. In the case of two level input pins, an internal pull-up resistor is present. This allows
a default value to be set when no external pull down resistor is connected between the pin and GND (by definition, a tri-level
input has a the default value of "M" (mid) if it is not connected). In order to connect a bi-directional pin to a non-default value, the
input must be connected to GND or VDD through an external pull-down/pull-up resistor. Note: when the output load presents a
low impedance in comparison to the internal pull-up resistor, the internal pull-up resistor may not be sufficient to pull the input up
to a logical “one”, and an external pull-up resistor may be required.
For bi-directional inputs, the external loading resistor between the pin and GND has to be sufficiently small (compared to the
internal pull-up resistor) so that the pin voltage be pulled below 0.8V (logical “zero”). In order to avoid loading effects when the
pin serves as output, the value of the external pull-down resistor should however be kept as large as possible. In general, it is
recommended to use an external resistor of around one sixth to one quarter of the internal pull-up resistor (see Application
Diagram). Note: when the output is used to drive a load presenting an small resistance between the output pin and VDD, this
resistance is in essence connected in parallel to the internal pull-up resistor. In such a case, the external pull-down resistor may
have to be dimensioned smaller to guarantee that the pin voltage will be low enough achieve the desired logical “zero”. This is
particularly true when driving 74FXX TTL components.
47745 Fremont Blvd., Fremont, California 94538 TEL (510) 492-0990 FAX (510) 492-0991
Rev 08/15/03 Page 2


Part Number PLL650-06
Description Network LAN Clock
Maker PhaseLink
Total Page 5 Pages
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