PLL650-08
Description
The PLL 650-08 is a low cost, low jitter, and high performance clock synthesizer. With PhaseLink’s proprietary analog Phase Locked Loop techniques, the chip accepts 25MHz crystal, and produces multiple output clocks for networking chips, and ASICs.
Key Features
- w w Full CMOS output swing with 40-mA output drive capability
- 25-mA output drive at TTL level
- Advanced, low power, sub-micron CMOS processes
- 25MHz fundamental crystal or clock input
- 1 output fixed at 100MHz , 1 output fixed at 125MHz
- Zero PPM synthesis error in all clocks
- Ideal for Network switches
- Available in 8-Pin 150mil SOIC
- at .D w h S a t e e 4U m o .c PRELIMINARY PLL650-08 Network LAN Clock Source
