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PhaseLink

PLL650-08 Datasheet Preview

PLL650-08 Datasheet

Network LAN Clock Source

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et4U.comFEATURES
heFull CMOS output swing with 40-mA output drive
taScapability. 25-mA output drive at TTL level.
aAdvanced, low power, sub-micron CMOS processes.
.D25MHz fundamental crystal or clock input.
1 output fixed at 100MHz , 1 output fixed at 125MHz .
wZero PPM synthesis error in all clocks.
wwIdeal for Network switches.
PRELIMINARY PLL650-08
Network LAN Clock Source
PIN CONFIGURATION
XIN
XOUT
GND
1
2
3
8 VDD
7 100MHz
6 GND
3.3V operation.
Available in 8-Pin 150mil SOIC.
mDESCRIPTIONS
.coThe PLL 650-08 is a low cost, low jitter, and high
performance clock synthesizer. With PhaseLink’s
proprietary analog Phase Locked Loop techniques, the chip
Uaccepts 25MHz crystal, and produces multiple output
clocks for networking chips, and ASICs.
VDD 4
5 125MHz
Sheet4BLOCK DIAGRAM
.DataXIN
wwwXOUT
XTAL
OSC
Control
Logic
100MHz
125MHz
www.DataSheet4U.com47745 Fremont Blvd., Fremont, California 94538 TEL (510) 492-0990 FAX (510) 492-0991
Rev 07/15/02 Page 1




PhaseLink

PLL650-08 Datasheet Preview

PLL650-08 Datasheet

Network LAN Clock Source

No Preview Available !

PIN DESCRIPTIONS
Name
XIN
XOUT
125MHz
100MHz
VDD
GND
Number
1
2
5
7
4,8
3,6
PRELIMINARY PLL650-08
Network LAN Clock Source
Type Description
I
25MHz fundamental crystal input (20pF CL parallel resonant). CL have been
integrated into the chip. No external CL capacitor is required.
O Crystal connection pin.
O 125MHz output.
O 100MHz output.
P 3.3V power supply
P Ground.
47745 Fremont Blvd., Fremont, California 94538 TEL (510) 492-0990 FAX (510) 492-0991
Rev 07/15/02 Page 2


Part Number PLL650-08
Description Network LAN Clock Source
Maker PhaseLink
Total Page 5 Pages
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