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PLL650-10 Datasheet Preview

PLL650-10 Datasheet

Network LAN Clock

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om PLL650-10PRELIMINARY
.c Network LAN Clock for Gigabit Ethernet
et4UFEATURES
heFull CMOS output swing with 40-mA output drive
taScapability. 25-mA output drive at TTL level.
aAdvanced, low power, sub-micron CMOS processes.
.D25MHz fundamental crystal or clock input.
Two outputs fixed at 125MHz..
wZero PPM synthesis error in all clocks.
wwIdeal for Network switches.
PIN CONFIGURATION
XIN
XO U T
GND
1
2
3
8 VDD
7 GND
6 VDD
3.3V operation.
Available in 8-Pin 150mil SOIC.
mDESCRIPTIONS
.coThe PLL 650-10 is a low cost, low jitter, and high
performance clock synthesizer. With PhaseLink’s
proprietary analog Phase Locked Loop techniques, the chip
Uaccepts 25MHz crystal, and produces multiple output
clocks for networking chips, and ASICs.
et4BLOCK DIAGRAM
taSheXIN
www.DaXOUT
XTAL
OSC
C o n tro l
Lo g ic
125MHz 4
5 125MHz
1 2 5 MHz
1 2 5 MHz
www.DataSheet4U.com47745 Fremont Blvd., Fremont, California 94538 TEL (510) 492-0990 FAX (510) 492-0991
Rev 12/10/02 Page 1




PhaseLink

PLL650-10 Datasheet Preview

PLL650-10 Datasheet

Network LAN Clock

No Preview Available !

PIN DESCRIPTIONS
Name
XIN
XOUT
125MHz
VDD
GND
Number
1
2
4,5
6,8
3,7
PRELIMINARY PLL650-10
Network LAN Clock for Gigabit Ethernet
Type Description
I
25MHz fundamental crystal input (20pF CL parallel resonant). CL have been
integrated into the chip. No external CL capacitor is required.
O Crystal connection pin.
O 125MHz outputs.
P 3.3V power supply
P Ground.
47745 Fremont Blvd., Fremont, California 94538 TEL (510) 492-0990 FAX (510) 492-0991
Rev 12/10/02 Page 2


Part Number PLL650-10
Description Network LAN Clock
Maker PhaseLink
Total Page 5 Pages
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