Datasheet4U Logo Datasheet4U.com

PLL650-10 Datasheet Network Lan Clock

Manufacturer: PhaseLink

Datasheet Details

Part number PLL650-10
Manufacturer PhaseLink
File Size 347.46 KB
Description Network LAN Clock
Datasheet PLL650-10_PhaseLink.pdf

General Description

S The PLL 650-10 is a low cost, low jitter, and high performance clock synthesizer.

With PhaseLink’s proprietary analog Phase Locked Loop techniques, the chip accepts 25MHz crystal, and produces multiple output clocks for networking chips, and ASICs.

BLOCK DIAGRAM XIN XO UT XTAL OS C w w w .D C ontrol Logic t a S a e h t e U 4 .c m o 125MHz 125MHz 47745 Fremont Blvd., Fremont, California 94538 TEL (510) 492-0990 FAX (510) 492-0991 w w w .D a t a e h S 4 t e U .

Key Features

  • w w Full CMOS output swing with 40-mA output drive capability. 25-mA output drive at TTL level. Advanced, low power, sub-micron CMOS processes. 25MHz fundamental crystal or clock input. Two outputs fixed at 125MHz. . Zero PPM synthesis error in all clocks. Ideal for Network switches. 3.3V operation. Available in 8-Pin 150mil SOIC. w . D at h S a t e e 4U . m o c.

More Datasheets from PhaseLink

Part Number Description
PLL650-02 Low EMI Network LAN Clock
PLL650-03 Low EMI Network LAN Clock
PLL650-04 Low EMI Clock
PLL650-05 Low EMI Network LAN Clock
PLL650-06 Network LAN Clock
PLL650-07 Low COST Network LAN Clock SOURCE
PLL650-08 Network LAN Clock Source
PLL650-09 Low Cost Network LAN Clock
PLL600-10 (PLL600-10/20/30) Ultra Low Current XO
PLL600-17 (PLL600-17/27/37) Ultra Low Current XO

PLL650-10 Distributor