Datasheet Details
| Part number | PLL650-07 |
|---|---|
| Manufacturer | PhaseLink |
| File Size | 380.26 KB |
| Description | Low COST Network LAN Clock SOURCE |
| Datasheet |
 PLL650-07 Datasheet
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General Description
The PLL 650-07 is a low cost, low jitter, and high performance clock synthesizer.
With PhaseLink’s proprietary analog Phase Locked Loop techniques, the chip accepts 25.0 MHz crystal, and produces multiple output clocks for networking chips, and ASICs.
Key Features
- w w w Full CMOS output swing with 40-mA output drive capability. 25-mA output drive at TTL level. Advanced, low power, sub-micron CMOS processes. 25MHz fundamental crystal or clock input. 2 outputs fixed at 50MHz, 2 outputs fixed at 25MHz . Zero PPM synthesis error in all clocks. Ideal for Network switches. 3.3V operation. Available in 14-Pin 150mil SOIC. . D at h S a t e e 4U . m o c.