S7A401830M sram equivalent, 128kx36 & 256kx18 sync-pipelined burst sram.
* VDD = 2.5V(2.3V ~ 2.7V) or 3.3V(3.1V ~ 3.5V) Power Supply
* VDDQ = 2.3V~2.7V I/O Power Supply (VDD=2.5V) or
2.3V~3.5V I/O Power Supply (VDD=3.3V)
* Synchron.
GW, BW, LBO, ZZ. Write cycles are internally selftimed and synchronous. Full bus-width write is done by GW, and each by.
The S7A403630M and S7A401830M are 4,718,592-bit Synchronous Static Random Access Memory designed for high performance. It is organized as 128K(256K) words of 36(18) bits and integrates address and control registers, a 2-bit burst address counter and .
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