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ZL30252 - Multiplier and Jitter Attenuator

General Description

5.

Key Features

  • Input Clocks.
  • Three inputs: two differential/CMOS, one CMOS.
  • Any input frequency from 1kHz to 1250MHz (1kHz to 300MHz for CMOS).
  • Inputs continually monitored for activity and frequency accuracy.
  • Automatic or manual reference switching.
  • Low-Bandwidth DPLL.
  • Programmable bandwidth, 14Hz to 500Hz.
  • Attenuates jitter up to several UI.
  • Freerun or digital hold on loss of all inputs.
  • Digitally controlled phase adju.

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Full PDF Text Transcription (Reference)

The following content is an automatically extracted verbatim text from the original manufacturer datasheet and is provided for reference purposes only.

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Register Map: Section 6.2 Features • Input Clocks • Three inputs: two differential/CMOS, one CMOS • Any input frequency from 1kHz to 1250MHz (1kHz to 300MHz for CMOS) • Inputs continually monitored for activity and frequency accuracy • Automatic or manual reference switching • Low-Bandwidth DPLL • Programmable bandwidth, 14Hz to 500Hz • Attenuates jitter up to several UI • Freerun or digital hold on loss of all inputs • Digitally controlled phase adjustment • Low-Jitter Fractional-N APLL and 3 Outputs • Any output frequency from <1Hz to 1035MHz • High-resolution fractional frequency conversion with 0ppm error • Easy-to-configure, encapsulated design requires no external VCXO or loop filter components • Each output has independent dividers • Output jitter is typically 0.16 to 0.