Description
Register Map: Section 6.2 .
9
5.
Features
* Input Clocks
* Three inputs: two differential/CMOS, one CMOS
* Any input frequency from 1kHz to 1250MHz (1kHz to 300MHz for CMOS)
* Inputs continually monitored for activity and frequency accuracy
* Automatic or manual reference switching
* Low-Bandw
Applications
* Frequency conversion, jitter attenuation and frequency synthesis in a wide variety of equipment types
IC1P, IC1N IC2P, IC2N IC3P/GPIO3
HSDIV1 HSDIV2 HSDIV3
Input Block
Divider, Monitor, Selector
Figure 10
XA
xtal
XB
driver ×2
DPLL
Jitter Filtering, Digital Hold
Figure 11
APLL
HSD
