Description
Register Map: Section 6.2 .
7
5.
External EE.
Features
* Four Input Clocks
* One crystal/CMOS input
* Two differential/CMOS inputs
* One single-ended/CMOS input
* Any input frequency from 9.72MHz to 1250MHz (9.72MHz to 300MHz for CMOS)
* Clock selection by pin or register control
* Low-Jitter Fractional-N APLL and 3 Outputs
Applications
* Frequency conversion and frequency synthesis in a wide variety of equipment types
IC1P, IC1N
HSDIV1
APLL
HSDIV1
DIV1
IC2P, IC2N
HSDIV2
~3.7 to 4.2GHz,
IC3P/GPIO3 XA
xtal
HSDIV3
NCO SS
Fractional-N Figure 6
HSDIV2
DIV2 DIV3
XB driver ×2
Microprocessor Port
(SPI or I2C Serial)