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IRF6729MTRPBF - Power MOSFET

Download the IRF6729MTRPBF datasheet PDF. This datasheet also covers the IRF6729MPBF variant, as both devices belong to the same power mosfet family and are provided as variant models within a single manufacturer datasheet.

Description

The IRF6729MPbF combines the latest HEXFET® Power MOSFET Silicon technology with the advanced DirectFET TM packaging to achieve the lowest on-state resistance in a package that has the footprint of a SO-8 and only 0.7 mm profile.

Features

  • ent (A) 100 100 10msec 10 DC 1 100µsec 1msec 10 T J = 150°C 1 T J = 25°C T J = -40°C VGS = 0V 0 0.0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0 VSD, Source-to-Drain Voltage (V) TA = 25°C TJ = 150°C Single Pulse 0.1 0.01 0.10 1.00 10.00 100.00 VDS, Drain-to-Source Voltage (V) Fig 10. Typical Source-Drain Diode Forward Voltage 200 Fig11. Maximum Safe Operating Area Typical VGS(th) Gate threshold Voltage (V) 2.4 ID, Drain Current (A) 150 2.2 2.0 ID = 10mA 1.8 100 50 1.6 0 25 50 75 100.

📥 Download Datasheet

Note: The manufacturer provides a single datasheet file (IRF6729MPBF-InternationalRectifier.pdf) that lists specifications for multiple related part numbers.

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Other Datasheets by International Rectifier (now Infineon)

Part Number Description
IRF6729MPBF Power MOSFET
IRF6720S2TR1PBF Power MOSFET
IRF6720S2TRPBF Power MOSFET
IRF6721SPBF Power MOSFET
IRF6721STRPBF Power MOSFET

Full PDF Text Transcription

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PD - 96229 HEXFET® Power MOSFET plus Schottky Diode ‚ RoHs Compliant and Halogen-Free  VDSS VGS RDS(on) RDS(on) l Integrated Monolithic Schottky Diode 30V max ±20V max 1.4mΩ@ 10V 2.2mΩ@ 4.5V l Low Profile (<0.7 mm) l Dual Sided Cooling Compatible  Qg tot Qgd Qgs2 Qrr Qoss Vgs(th) l Ultra Low Package Inductance 42nC 14nC 4.9nC 40nC 29nC 1.8V l Optimized for High Frequency Switching  l Ideal for CPU Core DC-DC Converters l Optimized for Sync. FET socket of Sync. Buck Converter l Low Conduction and Switching Losses l Compatible with existing Surface Mount Techniques  l 100% Rg tested DirectFET ™ ISOMETRIC MX Applicable DirectFET Outline and Substrate Outline (see p.
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