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IS46R86400D - 16Mx32 32Mx16 64Mx8 512Mb DDR SDRAM

Download the IS46R86400D datasheet PDF. This datasheet also covers the IS43R86400D variant, as both devices belong to the same 16mx32 32mx16 64mx8 512mb ddr sdram family and are provided as variant models within a single manufacturer datasheet.

Description

x8 A0-A12 A0-A9, A11 BA0, BA1 DQ0 DQ7 CK, CK CKE CS CAS RAS WE Row Address Input Column Address Input Bank Select Address Data I/O System Clock Input Clock Enable Chip Select Column Address Strobe Command Row Address Strobe Command Write Enable DM DQS VDD VDDQ VSS VSSQ VREF NC Data Writ

Features

  • VDD and VDDQ: 2.5V ± 0.2V (-6) VDD and VDDQ: 2.6V ± 0.1V (-5) SSTL_2 compatible I/O Double-data rate architecture; two data transfers per clock cycle Bidirectional, data strobe (DQS) is transmitted/ received with data, to be used in capturing data at the receiver DQS is edge-aligned with data for READs and centr.

📥 Download Datasheet

Note: The manufacturer provides a single datasheet file (IS43R86400D-IntegratedSiliconSolution.pdf) that lists specifications for multiple related part numbers.

📁 Similar Datasheet

Part Number Description Manufacturer
IS46R86400F 512Mb DDR SDRAM ISSI
IS46R83200B 256Mb DDR Synchronous DRAM ISSI
IS46R16160B 256Mb DDR Synchronous DRAM ISSI
IS46R16160D DDR SDRAM ISSI
IS46R16320F 512Mb DDR SDRAM ISSI

Other Datasheets by ISSI (now Infineon)

Part Number Description
IS46R16160F 256Mb DDR SDRAM
IS46R16320D 16Mx32 32Mx16 64Mx8 512Mb DDR SDRAM
IS46R16320E 512Mb DDR SDRAM
IS46R16800E 128Mb DDR SDRAM
IS46R32160D 16Mx32 32Mx16 64Mx8 512Mb DDR SDRAM

Full PDF Text Transcription (Reference)

The following content is an automatically extracted verbatim text from the original manufacturer datasheet and is provided for reference purposes only.

View original datasheet text
IS43/46R86400D IS43/46R16320D, IS43/46R32160D NOVEMBER 2012 16Mx32, 32Mx16, 64Mx8 512Mb DDR SDRAM FEATURES • • • • • • • • • • • • • • • • • VDD and VDDQ: 2.5V ± 0.2V (-6) VDD and VDDQ: 2.6V ± 0.1V (-5) SSTL_2 compatible I/O Double-data rate architecture; two data transfers per clock cycle Bidirectional, data strobe (DQS) is transmitted/ received with data, to be used in capturing data at the receiver DQS is edge-aligned with data for READs and centre-aligned with data for WRITEs Differential clock inputs (CK and CK) DLL aligns DQ and DQS transitions with CK transitions Commands entered on each positive CK edge; data and data mask referenced to both edges of DQS Four internal banks for concurrent operation Data Mask for write data.
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