IDT5T905 terabuffer equivalent, 2.5v single data rate 1:5 clock buffer terabuffer.
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IDT5T905
DESCRIPTION:
Guaranteed Low Skew < 25ps (max) Very low duty cycle distortion High speed propagation del.
FUNCTIONAL BLOCK DIAGRAM
TxS GL G
OUTPUT CONTROL
Q1
RxS A A/VREF
OUTPUT CONTROL
Q2
OUTPUT CONTROL
Q3
OUTPUT CON.
Guaranteed Low Skew < 25ps (max) Very low duty cycle distortion High speed propagation delay < 2.5ns. (max) Up to 250MHz operation Very low CMOS power levels 1.5V VDDQ for HSTL interface Hot insertable and over-voltage tolerant inputs 3-level input.
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