IDT5T9310 ii equivalent, 2.5v lvds 1:10 clock buffer terabuffer ii.
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IDT5T9310
DESCRIPTION:
Guaranteed Low Skew < 25ps (max) Very low duty cycle distortion < 125ps (max).
* Clock distribution
FUNCTIONAL BLOCK DIAGRAM
GL G1
OUTPUT CONTROL
Q1 Q1
PD
OUTPUT CONTROL
Q2 Q2
A1 A1
1
OU.
Guaranteed Low Skew < 25ps (max) Very low duty cycle distortion < 125ps (max) High speed propagation delay < 1.75ns (max) Up to 1GHz operation Selectable inputs Hot insertable and over-voltage tolerant inputs 3.3V / 2.5V LVTTL, HSTL, eHSTL, LVEPECL.
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