IS61NVVP25672 - (IS61NVVP25672 / IS61NVVP51236) STATE BUS SRAM

ISSI

IS61NVVP25672 Datasheet Preview — Preview of IS61NVVP25672 PDF

Datasheet Details

Part number	IS61NVVP25672
Manufacturer	ISSI
File Size	215.40 KB
Description	(IS61NVVP25672 / IS61NVVP51236) STATE BUS SRAM
Datasheet	IS61NVVP25672_ISSI.pdf

IS61NVVP25672 Product details

Description

® Byte Write Control Single R/W (Read/Write) control pin Clock controlled, registered address, data and control Interleaved or linear burst sequence control using MODE input Power Down mode Common data inputs and data outputs CKE pin to enable clock and suspend operation JEDEC 119-ball PBGA (x36) and 209-ball (x72) PBGA packages Single +1.8V (± 5%) power supply JTAG Boundary Scan Industrial tem

Features

100 percent bus utilization.
No wait cycles between Read and Write.
Internal self-timed write cycle www. DataSheet4U. com.
Individual ISSI.

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Other Datasheets by ISSI

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Published: Jul 12, 2008 |