* Flexible & Efficient Memory Architecture - Memory Cell: 1bit/Memory Cell - Organization: 512Mb x8, 256Mb x16 - Page Size for x8: (4K + 256) Bytes - Page Size for x1.

The device has 4352-byte static registers which allow program and read data to be transferred between the register and the memory cell array in 4352-byte increments. The Erase operation is implemented in a single block unit (256Kbytes + 16Kbytes). Da.

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