EDJ4208EFBG Features
* Double-data-rate architecture: two data transfers per clock cycle
* The high-speed data transfer is realized by the 8 bits prefetch pipelined architecture
* Bi-directional differential data strobe (DQS and /DQS) is transmitted/received with data for capturing data at the re
EDJ4208EFBG, EDJ4204EFBG Datasheet
Datasheet Details
EDJ4208EFBG, EDJ4204EFBG
Elpida Memory
392.78 KB
512m words x 8 bits 4g bits ddr3l sdram.
This datasheet PDF includes multiple part numbers: EDJ4208EFBG, EDJ4204EFBG.
Please refer to the document for exact specifications by model.
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EDJ4208EFBG Distributor
