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PA7540 - PA7540 PEEL Array Programmable Electrically Erasable Logic

Download the PA7540 datasheet PDF. This datasheet also covers the PA7 variant, as both devices belong to the same pa7540 peel array programmable electrically erasable logic family and are provided as variant models within a single manufacturer datasheet.

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Note: The manufacturer provides a single datasheet file (PA7-540.pdf) that lists specifications for multiple related part numbers.

Datasheet Details

Part number PA7540
Manufacturer Unknown Manufacturer
File Size 239.25 KB
Description PA7540 PEEL Array Programmable Electrically Erasable Logic
Datasheet download datasheet PA7540 Datasheet

General Description

The PA7540 is a member of the Programmable Electrically Erasable Logic (

Overview

PA7540 PEEL Array™ Programmable Electrically Erasable Logic Array Most Powerful 24-pin PLD Available - 20 I/Os, 2 inputs/clocks, 40 registers/latches - 40 logic cell output functions - PLA structure with true product-term sharing - Logic functions and registers can be I/O-buried Ideal for Combinatorial, Synchronous and Asynchronous Logic Applications - Integration of multiple PLDs and random logic - Buried counters, complex state-machines - Comparators, decoders, multiplexers and other widegate functions High-Speed Commercial and Industrial Versions - As fast as 10ns/15ns (tpdi/tpdx), 71.4MHz (fMAX) - Industrial grade available for 4.5 to 5.

Key Features

  • - Independent or global clocks, resets, presets, clock polarity and output enables - Sum-of-products logic for output enables Development and Programmer Support - Anachip’s WinPLACE Development Software - Fitters for ABEL, CUPL and other software - Programming support by popular third-party programmers presets, clock polarity, and other features, making the PA7540 suitable for a variety of combinatorial, synchronous and asynchronous logic.

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