* LD-MOS Technology with the Lowest Figure of Merit: RDS(on) = 8.2mΩ to Minimize On-State Losses Qg = 8.1nC for Ultra-Fast Switching
* Vgs(th) = -0.8V typ. for a .

* DC-DC Converters
* Battery Management
* Load Switch Mechanical Data
* Case: U-WLB1515-9
* Termina.

This 3rd generation Lateral MOSFET (LD-MOS) is engineered to minimize on-state losses and switch ultra-fast, making it ideal for high efficiency power transfer. It uses Chip-Scale Package (CSP) to increase power density by combining low thermal imped.

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