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CY7C1482BV33 - (CY7C148xBV33) 72-Mbit (2M x 36/4M x 18/1M x 72) Pipelined Sync SRAM

Download the CY7C1482BV33 datasheet PDF. This datasheet also covers the CY7C1480BV33 variant, as both devices belong to the same (cy7c148xbv33) 72-mbit (2m x 36/4m x 18/1m x 72) pipelined sync sram family and are provided as variant models within a single manufacturer datasheet.

Description

The CY7C1480BV33, CY7C1482BV33, and CY7C1486BV33 SRAM integrates 2M x 36/4M x 18/1M × 72 SRAM cells with advanced synchronous peripheral circuitry and a 2-bit counter for internal burst operation.

Features

  • Functional.

📥 Download Datasheet

Note: The manufacturer provides a single datasheet file (CY7C1480BV33_CypressSemiconductor.pdf) that lists specifications for multiple related part numbers.

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Other Datasheets by Cypress (Infineon)

Part Number Description
CY7C1482BV25 (CY7C148xBV25) 72-Mbit (2M x 36/4M x 18/1M x 72) Pipelined Sync SRAM
CY7C1482V33 (CY7C1480V33 / CY7C1482V33 / CY7C1486V33) 72-Mbit (2M x 36/4M x 18/1M x 72) Pipelined Sync SRAM
CY7C148 (CY7C148 / CY7C149) 1K x 4 Static RAM
CY7C1480BV25 72-Mbit (2M x 36/4M x 18/1M x 72) Pipelined Sync SRAM
CY7C1480BV33 (CY7C148xBV33) 72-Mbit (2M x 36/4M x 18/1M x 72) Pipelined Sync SRAM

Full PDF Text Transcription

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CY7C1480BV33 CY7C1482BV33, CY7C1486BV33 72-Mbit (2M x 36/4M x 18/1M x 72) Pipelined Sync SRAM Features ■ ■ ■ ■ ■ ■ Functional Description The CY7C1480BV33, CY7C1482BV33, and CY7C1486BV33 SRAM integrates 2M x 36/4M x 18/1M × 72 SRAM cells with advanced synchronous peripheral circuitry and a 2-bit counter for internal burst operation. All synchronous inputs are gated by registers controlled by a positive-edge-triggered Clock Input (CLK). The synchronous inputs include all addresses, all data inputs, address-pipelining Chip Enable (CE1), depth-expansion Chip Enables (CE2 and CE3), Burst Control inputs (ADSC, ADSP, and ADV), Write Enables (BWX, and BWE), and Global Write (GW). Asynchronous inputs include the Output Enable (OE) and the ZZ pin.
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