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Cypress Semiconductor Electronic Components Datasheet

CY7C1480BV33 Datasheet

(CY7C148xBV33) 72-Mbit (2M x 36/4M x 18/1M x 72) Pipelined Sync SRAM

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CY7C1480BV33
CY7C1482BV33, CY7C1486BV33
72-Mbit (2M x 36/4M x 18/1M x 72)
Pipelined Sync SRAM
Features
Supports bus operation up to 250 MHz
Available speed grades are 250, 200, and 167 MHz
Registered inputs and outputs for pipelined operation
3.3V core power supply
2.5V/3.3V IO operation
Fast clock-to-output times
3.0 ns (for 250 MHz device)
Provide high performance 3-1-1-1 access rate
User selectable burst counter supporting Intel®
Pentium® interleaved or linear burst sequences
Separate processor and controller address strobes
Synchronous self timed writes
Asynchronous output enable
Single cycle chip deselect
CY7C1480BV33, CY7C1482BV33 available in
JEDEC-standard Pb-free 100-pin TQFP, Pb-free and
non Pb-free 165-ball FBGA package. CY7C1486BV33
available in Pb-free and non-Pb-free 209-ball FBGA package
IEEE 1149.1 JTAG-Compatible Boundary Scan
“ZZ” Sleep Mode option
Functional Description
The CY7C1480BV33, CY7C1482BV33, and CY7C1486BV33
SRAM integrates 2M x 36/4M x 18/1M × 72 SRAM cells with
advanced synchronous peripheral circuitry and a 2-bit counter
for internal burst operation. All synchronous inputs are gated by
registers controlled by a positive-edge-triggered Clock Input
(CLK). The synchronous inputs include all addresses, all data
inputs, address-pipelining Chip Enable (CE1), depth-expansion
Chip Enables (CE2 and CE3), Burst Control inputs (ADSC,
ADSP, and ADV), Write Enables (BWX, and BWE), and Global
Write (GW). Asynchronous inputs include the Output Enable
(OE) and the ZZ pin.
Addresses and chip enables are registered at the rising edge of
the clock when either Address Strobe Processor (ADSP) or
Address Strobe Controller (ADSC) are active. Subsequent burst
addresses may be internally generated as controlled by the
Advance pin (ADV).
Address, data inputs, and write controls are registered on-chip
to initiate a self timed write cycle.This part supports byte write
operations (see sections Pin Definitions on page 7 and Truth
Table on page 10 for further details). Write cycles can be one to
two or four bytes wide as controlled by the byte write control
inputs. GW when active LOW causes all bytes to be written.
The CY7C1480BV33, CY7C1482BV33, and CY7C1486BV33
operates from a +3.3V core power supply while all outputs may
operate with either a +2.5 or +3.3V supply. All inputs and outputs
are JEDEC standard JESD8-5 compatible. For best practices
recommendations, refer to the Cypress application note AN1064
“SRAM System Guidelines”.
Selection Guide
Description
Maximum Access Time
Maximum Operating Current
Maximum CMOS Standby Current
250 MHz
3.0
500
120
200 MHz
3.0
500
120
167 MHz
3.4
450
120
Unit
ns
mA
mA
Cypress Semiconductor Corporation • 198 Champion Court
Document #: 001-15145 Rev. *A
www.DataSheet.in
• San Jose, CA 95134-1709 • 408-943-2600
Revised March 05, 2008
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Cypress Semiconductor Electronic Components Datasheet

CY7C1480BV33 Datasheet

(CY7C148xBV33) 72-Mbit (2M x 36/4M x 18/1M x 72) Pipelined Sync SRAM

No Preview Available !

CY7C1480BV33
CY7C1482BV33, CY7C1486BV33
Logic Block Diagram – CY7C1480BV33 (2M x 36)
A 0, A1, A
MODE
ADV
CLK
ADSC
ADSP
BW D
BW C
BW B
BW A
BWE
GW
CE 1
CE 2
CE 3
OE
ADDRESS
REGISTER
2 A [1:0]
Q1
BURST
COUNTER
CLR AND Q0
LOGIC
DQ D ,DQP D
BYTE
WRITE REGISTER
DQ C ,DQP C
BYTE
WRITE REGISTER
DQ B ,DQP B
BYTE
WRITE REGISTER
DQ A ,DQP A
BYTE
WRITE REGISTER
ENABLE
REGISTER
PIPELINED
ENABLE
DQ D ,DQPD
BYTE
WRITE DRIVER
DQ C ,DQP C
BYTE
WRITE DRIVER
DQ B ,DQP B
BYTE
WRITE DRIVER
DQ A ,DQP A
BYTE
WRITE DRIVER
MEMORY
ARRAY
SENSE
AMPS
OUTPUT
REGISTERS
OUTPUT
BUFFERS
E
DQs
DQP A
DQP B
DQP C
DQP D
INPUT
REGISTERS
ZZ SLEEP
CONTROL
Logic Block Diagram – CY7C1482BV33 (4M x 18)
A0, A1, A
MODE
ADV
CLK
ADSC
ADSP
BW B
BW A
BWE
GW
CE 1
CE2
CE3
OE
ADDRESS
REGISTER
2 A[1:0]
BURST Q1
COUNTER AND
LOGIC
CLR Q0
DQ B,DQP B
WRITE REGISTER
DQ A, DQP A
WRITE REGISTER
ENABLE
REGISTER
PIPELINED
ENABLE
DQ B,DQP B
WRITE DRIVER
DQ A, DQP A
WRITE DRIVER
MEMORY
ARRAY
SENSE OUTPUT
AMPS REGISTERS
OUTPUT
BUFFERS
E
DQs
DQP A
DQP B
INPUT
REGISTERS
ZZ SLEEP
CONTROL
Document #: 001-15145 Rev. *A
Page 2 of 34
www.DataSheet.in
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Part Number CY7C1480BV33
Description (CY7C148xBV33) 72-Mbit (2M x 36/4M x 18/1M x 72) Pipelined Sync SRAM
Maker Cypress Semiconductor
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