2M x 36/4M x 18/1M x 72 Flow-through SRAM
• Supports 133-MHz bus operations
• 2M x 36/4M x 18/1M x 72 common I/O
• Fast clock-to-output times
— 5.5 ns (for 150-MHz device)
— 6.5 ns (for 133-MHz device)
— 7.5 ns (for 117-MHz device)
— 8.5 ns (for 100-MHz device)
• Single 3.3V –5% and +5% power supply VDD
• Separate VDDQ for 3.3V or 2.5V
• Byte Write Enable and Global Write control
• Burst Capability—linear or interleaved burst order
• Automatic power-down available using ZZ mode or CE
• JTAG boundary scan for BGA packaging version
• Available in 119-ball bump BGA and 100-pin TQFP
packages (CY7C1481V33 and CY7C1483V33). 209 BGA
package for CY7C1487V33
• 165-ball FBGA and 209-ball BGA will only be offered on
an opportunity basis (check with Cypress sales and
The Cypress Synchronous Burst SRAM family employs
high-speed, low power CMOS designs using advanced
single-layer polysilicon, triple-layer metal technology. Each
memory cell consists of six transistors.
The CY7C1481V33/CY7C1483V33/CY7C1487V33 SRAMs
integrate 2,097,152 x 36 / 4,194,304 x18 and 1,048,576x 72
SRAM cells with advanced synchronous peripheral circuitry
and a 2-bit counter for internal burst operation. All
synchronous inputs are gated by registers controlled by a
positive-edge-triggered clock input (CLK). The synchronous
inputs include all addresses, all data inputs, address-pipelining
Chip Enable (CE), Burst Control Inputs (ADSC, ADSP, and
ADV), Write Enables (BWa, BWb, BWc, BWd, BWe, BWf, BWg
and BWh, BWE), and Global Write (GW).
Asynchronous inputs include the Output Enable (OE) and
Burst Mode Control (MODE). The data outputs (Q), enabled
by OE, are also asynchronous.
Addresses and chip enables are registered with either
Address Status Processor (ADSP) or address status controller
(ADSC) input pins. Subsequent burst addresses can be inter-
nally generated as controlled by the Burst Advance Pin (ADV).
Address, data inputs, and write controls are registered on-chip
to initiate self-timed WRITE cycle. WRITE cycles can be one
to four bytes wide as controlled by the write control inputs.
Individual byte write allows individual byte to be written. BWa
controls DQa and DPa. BWb controls DQb and DPb. BWc
controls DQc and DPc. BWd controls DQd and DPd. BWe
controls DQe and DPe. BWf controls DQf and DPf. BWg
controls DQg and DPg. BWh controls DQh and DPh. BWa,
BWb, BWc, BWd, BWe, BWf, BWg, and BWh can be active only
with BWE LOW. GW being LOW causes all bytes to be written.
WRITE pass-through capability allows written data available at
the output for the immediately next READ cycle. This device
also incorporates pipelined enable circuit for easy depth
expansion without penalizing system performance.
Inputs and outputs of the CY7C1481V33/CY7C1483V33/
CY7C1487V33 are JEDEC-standard JESD8-5-compatible.
Cypress Semiconductor Corporation • 3901 North First Street • San Jose, CA 95134 • 408-943-2600
Document #: 38-05284 Rev. *A
Revised January 18, 2003