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Cypress Semiconductor Electronic Components Datasheet

CY7C1480BV25 Datasheet

72-Mbit (2M x 36/4M x 18/1M x 72) Pipelined Sync SRAM

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CY7C1480BV25
72-Mbit (2M × 36) Pipelined Sync SRAM
72-Mbit (2M × 36) Pipelined Sync SRAM
Features
Supports bus operation up to 250 MHz
Available speed grades are 250, 200, and 167 MHz
Registered inputs and outputs for pipelined operation
2.5 V core power supply
2.5 V I/O operation
Fast clock-to-output time
3.0 ns (for 250 MHz device)
Provide high performance 3-1-1-1 access rate
User selectable burst counter supporting Intel® Pentium®
interleaved or linear burst sequences
Separate processor and controller address strobes
Synchronous self timed writes
Asynchronous output enable
Single cycle chip deselect
CY7C1480BV25 available in JEDEC-standard Pb-free 100-pin
thin quad flat pack (TQFP), Pb-free and non Pb-free 165-ball
fine-pitch ball grid array (FBGA) package.
IEEE 1149.1 JTAG-Compatible Boundary Scan
“ZZ” sleep mode option
Functional Description
The CY7C1480BV25 SRAM integrates 2M × 36 SRAM cells with
advanced synchronous peripheral circuitry and a two-bit counter
for internal burst operation. All synchronous inputs are gated by
registers controlled by a positive-edge-triggered Clock Input
(CLK). The synchronous inputs include all addresses, all data
inputs, address-pipelining Chip Enable (CE1), depth-expansion
Chip Enables (CE2 and CE3), Burst Control inputs (ADSC,
ADSP, and ADV), Write Enables (BWX, and BWE), and Global
Write (GW). Asynchronous inputs include the Output Enable
(OE) and the ZZ pin.
Addresses and chip enables are registered at rising edge of
clock when either Address Strobe Processor (ADSP) or Address
Strobe Controller (ADSC) is active. Subsequent burst addresses
can be internally generated as controlled by the Advance pin
(ADV).
Address, data inputs, and write controls are registered on-chip
to initiate a self timed Write cycle. This part supports Byte Write
operations (see Pin Definitions on page 6 and Truth Table on
page 9 for further details). Write cycles can be one to two or four
bytes wide, as controlled by the byte write control inputs. When
it is active LOW, GW writes all bytes.
For a complete list of related documentation, click here.
Selection Guide
Description
Maximum access time
Maximum operating current
Maximum complementary metal oxide semiconductor (CMOS) standby current
250 MHz
3.0
450
120
200 MHz
3.0
450
120
167 MHz
3.4
400
120
Unit
ns
mA
mA
Cypress Semiconductor Corporation • 198 Champion Court
Document Number: 001-15143 Rev. *N
• San Jose, CA 95134-1709 • 408-943-2600
Revised June 13, 2016


Cypress Semiconductor Electronic Components Datasheet

CY7C1480BV25 Datasheet

72-Mbit (2M x 36/4M x 18/1M x 72) Pipelined Sync SRAM

No Preview Available !

CY7C1480BV25
Logic Block Diagram – CY7C1480BV25
A 0, A1, A
MODE
ADV
CLK
ADSC
ADSP
BW D
BW C
BW B
BW A
BWE
GW
CE 1
CE 2
CE 3
OE
ZZ
ADDRESS
REGISTER
2 A [1:0]
Q1
BURST
COUNTER
CLR AND Q0
LOGIC
DQ D ,DQP D
BYTE
WRITE REGISTER
DQ C ,DQP C
BYTE
WRITE REGISTER
DQ B ,DQP B
BYTE
WRITE REGISTER
DQ A ,DQP A
BYTE
WRITE REGISTER
ENABLE
REGISTER
PIPELINED
ENABLE
DQ D ,DQPD
BYTE
WRITE DRIVER
DQ C ,DQP C
BYTE
WRITE DRIVER
DQ B ,DQP B
BYTE
WRITE DRIVER
DQ A ,DQP A
BYTE
WRITE DRIVER
SLEEP
CONTROL
MEMORY
ARRAY
SENSE
AMPS
OUTPUT
REGISTERS
OUTPUT
BUFFERS
E
DQs
DQP A
DQP B
DQP C
DQP D
INPUT
REGISTERS
Document Number: 001-15143 Rev. *N
Page 2 of 33


Part Number CY7C1480BV25
Description 72-Mbit (2M x 36/4M x 18/1M x 72) Pipelined Sync SRAM
Maker Cypress Semiconductor
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