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CY7C1481V33 - (CY7C1481V33 / CY7C1483V33 / CY7C1487V33) 2M x 36/4M x 18/1M x 72 Flow-Through SRAM

Description

The Cypress Synchronous Burst SRAM family employs high-speed, low power CMOS designs using advanced single-layer polysilicon, triple-layer metal technology.

Each memory cell consists of six transistors.

Features

  • Supports 133-MHz bus operations.
  • 2M x 36/4M x 18/1M x 72 common I/O.
  • Fast clock-to-output times.
  • 5.5 ns (for 150-MHz device).
  • 6.5 ns (for 133-MHz device).
  • 7.5 ns (for 117-MHz device).
  • 8.5 ns (for 100-MHz device).
  • Single 3.3V.
  • 5% and +5% power supply VDD.
  • Separate VDDQ for 3.3V or 2.5V.
  • Byte Write Enable and Global Write control.
  • Burst Capability.
  • linear or interleaved burst order.

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Datasheet Details

Part number CY7C1481V33
Manufacturer Cypress (Infineon)
File Size 612.36 KB
Description (CY7C1481V33 / CY7C1483V33 / CY7C1487V33) 2M x 36/4M x 18/1M x 72 Flow-Through SRAM
Datasheet download datasheet CY7C1481V33 Datasheet

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Full PDF Text Transcription (Reference)

The following content is an automatically extracted verbatim text from the original manufacturer datasheet and is provided for reference purposes only.

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PRELIMINARY CY7C1481V33 CY7C1483V33 CY7C1487V33 2M x 36/4M x 18/1M x 72 Flow-through SRAM Features • Supports 133-MHz bus operations • 2M x 36/4M x 18/1M x 72 common I/O • Fast clock-to-output times — 5.5 ns (for 150-MHz device) — 6.5 ns (for 133-MHz device) — 7.5 ns (for 117-MHz device) — 8.5 ns (for 100-MHz device) • Single 3.3V –5% and +5% power supply VDD • Separate VDDQ for 3.3V or 2.5V • Byte Write Enable and Global Write control • Burst Capability—linear or interleaved burst order • Automatic power-down available using ZZ mode or CE deselect • JTAG boundary scan for BGA packaging version • Available in 119-ball bump BGA and 100-pin TQFP packages (CY7C1481V33 and CY7C1483V33).
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