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CY7C1481V25 - 72-Mbit (2M x 36/4M x 18/1M x 72) Flow-Through SRAM

Download the CY7C1481V25 datasheet PDF. This datasheet also covers the CY7C1487V25 variant, as both devices belong to the same 72-mbit (2m x 36/4m x 18/1m x 72) flow-through sram family and are provided as variant models within a single manufacturer datasheet.

Description

The CY7C1481V25/CY7C1483V25/CY7C1487V25 is a 2.5V, 2M x 36/4M x 18/1M x 72 Synchronous Flow-through SRAM designed to interface with high-speed microprocessors with minimum glue logic.

Maximum access delay from clock rise is 6.5 ns (133-MHz version).

Features

  • Supports 133 MHz bus operations 2M x 36/4M x 18/1M x 72 common IO 2.5V core power supply (VDD) 2.5V or 1.8V IO supply (VDDQ) Fast clock-to-output time Functional.

📥 Download Datasheet

Note: The manufacturer provides a single datasheet file (CY7C1487V25_CypressSemiconductor.pdf) that lists specifications for multiple related part numbers.

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Other Datasheets by Cypress (Infineon)

Part Number Description
CY7C1481V33 (CY7C1481V33 / CY7C1483V33 / CY7C1487V33) 2M x 36/4M x 18/1M x 72 Flow-Through SRAM
CY7C148 (CY7C148 / CY7C149) 1K x 4 Static RAM
CY7C1480BV25 72-Mbit (2M x 36/4M x 18/1M x 72) Pipelined Sync SRAM
CY7C1480BV33 (CY7C148xBV33) 72-Mbit (2M x 36/4M x 18/1M x 72) Pipelined Sync SRAM
CY7C1480V33 (CY7C1480V33 / CY7C1482V33 / CY7C1486V33) 72-Mbit (2M x 36/4M x 18/1M x 72) Pipelined Sync SRAM

Full PDF Text Transcription (Reference)

The following content is an automatically extracted verbatim text from the original manufacturer datasheet and is provided for reference purposes only.

View original datasheet text
CY7C1481V25 CY7C1483V25 CY7C1487V25 72-Mbit (2M x 36/4M x 18/1M x 72) Flow-Through SRAM Features • • • • • Supports 133 MHz bus operations 2M x 36/4M x 18/1M x 72 common IO 2.5V core power supply (VDD) 2.5V or 1.8V IO supply (VDDQ) Fast clock-to-output time Functional Description[1] The CY7C1481V25/CY7C1483V25/CY7C1487V25 is a 2.5V, 2M x 36/4M x 18/1M x 72 Synchronous Flow-through SRAM designed to interface with high-speed microprocessors with minimum glue logic. Maximum access delay from clock rise is 6.5 ns (133-MHz version). A 2-bit on-chip counter captures the first address in a burst and increments the address automatically for the rest of the burst access. All synchronous inputs are gated by registers controlled by a positive edge triggered Clock Input (CLK).
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