CY7C1412V18 Key Features
- Separate Independent Read and Write data ports
- Supports concurrent transactions
- 200-MHz clock for high bandwidth
- 2-Word Burst on all accesses
- Double Data Rate (DDR) interfaces on both Read and Write ports (data transferred at 400 MHz) @ 200 MHz
- Two input clocks (K and K) for precise DDR timing
- SRAM uses rising edges only
- Two output clocks (C and C) accounts for clock skew and flight time mismatching
- Echo clocks (CQ and CQ) simplify data capture in high-speed systems
- Single multiplexed address input bus latches address inputs for both Read and Write ports