CY7C1412AV18 architecture equivalent, (cy7c14xxav18) 36-mbit qdr-ii sram 2-word burst architecture.
* Separate Independent Read and Write data ports — Supports concurrent transactions
* 250-MHz clock for high bandwidth
* 2-Word Burst on all accesses
* Do.
The CY7C1410AV18, CY7C1425AV18, CY7C1412AV18, and CY7C1414AV18 are 1.8V Synchronous Pipelined SRAMs, equipped with QDR™-II architecture. QDR-II architecture consists of two separate ports to access the memory array. The Read port has dedicated Data O.
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