Datasheet Details
| Part number | CY7C1410AV18 |
|---|---|
| Manufacturer | Cypress (Infineon) |
| File Size | 1.19 MB |
| Description | (CY7C14xxAV18) 36-Mbit QDR-II SRAM 2-Word Burst Architecture |
| Datasheet |
 CY7C1410AV18 Datasheet
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Description
The CY7C1410AV18, CY7C1425AV18, CY7C1412AV18, and CY7C1414AV18 are 1.8V Synchronous Pipelined SRAMs, equipped with QDR™-II architecture.
QDR-II architecture consists of two separate ports to access the memory array.
Features
- Separate Independent Read and Write data ports.
- Supports concurrent transactions.
- 250-MHz clock for high bandwidth.
- 2-Word Burst on all accesses.
- Double Data Rate (DDR) interfaces on both Read and Write www. DataSheet4U. com ports (data transferred at 500 MHz) @ 250 MHz.
- Two input clocks (K and K) for precise DDR timing.
- SRAM uses rising edges only.
- Two input clocks for output data (C and C) to minimize clock skew and flight-.