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CY7C1387C - (CY7C1386C / CY7C1387C) 18-Mb (512K x 36/1M x 18) Pipelined DCD Sync SRAM

This page provides the datasheet information for the CY7C1387C, a member of the CY7C1386C (CY7C1386C / CY7C1387C) 18-Mb (512K x 36/1M x 18) Pipelined DCD Sync SRAM family.

Description

The CY7C1386C/CY7C1387C SRAM integrates 524,288 x 36 and 1048,576 x 18 SRAM cells with advanced synchronous peripheral circuitry and a two-bit counter for internal burst operation.

All synchronous inputs are gated by registers controlled by a positive-edge-triggered Clock Input (CLK).

Features

  • Supports bus operation up to 250 MHz.
  • Available speed grades are 250, 225, 200 and 167 MHz.
  • Registered inputs and outputs for pipelined operation.
  • Optimal for performance (Double-Cycle deselect).
  • Depth expansion without wait state.
  • 3.3V.
  • 5% and +10% core power supply (VDD).
  • 2.5V / 3.3V I/O operation.
  • Fast clock-to-output times.
  • 2.6 ns (for 250-MHz device).
  • 2.8 ns (for 225-MHz device).
  • 3.0.

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Datasheet preview – CY7C1387C

Datasheet Details

Part number CY7C1387C
Manufacturer Cypress (now Infineon)
File Size 731.23 KB
Description (CY7C1386C / CY7C1387C) 18-Mb (512K x 36/1M x 18) Pipelined DCD Sync SRAM
Datasheet download datasheet CY7C1387C Datasheet
Additional preview pages of the CY7C1387C datasheet.

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Full PDF Text Transcription

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www.DataSheet4U.com CY7C1386C CY7C1387C 18-Mb (512K x 36/1M x 18) Pipelined DCD Sync SRAM Features • Supports bus operation up to 250 MHz • Available speed grades are 250, 225, 200 and 167 MHz • Registered inputs and outputs for pipelined operation • Optimal for performance (Double-Cycle deselect) • Depth expansion without wait state • 3.3V –5% and +10% core power supply (VDD) • 2.5V / 3.3V I/O operation • Fast clock-to-output times — 2.6 ns (for 250-MHz device) — 2.8 ns (for 225-MHz device) — 3.0 ns (for 200-MHz device) — 3.
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