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CY7C1386S - 18-Mbit (512 K x 36) Pipelined DCD Sync SRAM

Description

The CY7C1386S SRAM integrates 512 K × 36 SRAM cells with advanced synchronous peripheral circuitry and a two-bit counter for internal burst operation.

All synchronous inputs are gated by registers controlled by a positive edge triggered clock input (CLK).

Features

  • Supports bus operation up to 167 MHz.
  • Available speed grade is 167 MHz.
  • Registered inputs and outputs for pipelined operation.
  • Optimal for performance (double-cycle deselect).
  • Depth expansion without wait state.
  • 3.3 V core power supply (VDD).
  • 2.5 V or 3.3 V I/O power supply (VDDQ).
  • Fast clock-to-output times.
  • 3.4 ns (for 167 MHz device).
  • Provides high-performance 3-1-1-1 access rate.
  • User selectable burst counter supporting Intel Pentium.

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CY7C1386S 18-Mbit (512 K × 36) Pipelined DCD Sync SRAM 18-Mbit (512 K × 36) Pipelined DCD Sync SRAM Features ■ Supports bus operation up to 167 MHz ■ Available speed grade is 167 MHz ■ Registered inputs and outputs for pipelined operation ■ Optimal for performance (double-cycle deselect) ■ Depth expansion without wait state ■ 3.3 V core power supply (VDD) ■ 2.5 V or 3.3 V I/O power supply (VDDQ) ■ Fast clock-to-output times ❐ 3.
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